1. Field
Example embodiments relate to a semiconductor package, and more particularly, to a semiconductor package including a semiconductor chip on which a chip alignment mark may be formed.
2. Description of the Related Art
Various semiconductor package structures have been suggested for realizing a highly precise and compact semiconductor package. Particularly, research is focusing on a stacked package structure in which bumps formed on a surface of a semiconductor chip are bonded to wiring patterns formed on a surface of a substrate.
FIG. 1 is a plan view illustrating the structure of a semiconductor chip 11 of a conventional semiconductor package, and FIG. 2 is a plan view illustrating a substrate 21 of a conventional semiconductor package. FIG. 3 is a plan view illustrating the semiconductor chip 11 stacked on the substrate 21 of the conventional semiconductor package.
FIG. 1 illustrates a portion of the semiconductor chip 11 of a conventional semiconductor package. As shown in FIG. 1, a semiconductor chip 11 may include a plurality of bumps 12a and 12b disposed on the outer regions of the semiconductor chip 11. The semiconductor chip 11 may also include a chip alignment mark 15 to precisely dispose the semiconductor chip 11 on the substrate in a correct position. The chip alignment mark 15 may also be surrounded by an auxiliary line 14.
The bumps 12b may be dummy bumps which do not electrically connect the semiconductor chip 11 to the substrate 21. The bumps 12a, however, may electrically connect the semiconductor chip 11 to the substrate 21. Routing wirings may be formed on the semiconductor chip 11, which may extend toward a center of the semiconductor chip 11. The routing wirings may be formed to electrically connect the bumps 12a to a semiconductor device (not shown). The bumps 12a and 12b and the chip alignment mark 15 may be formed on a lower surface of the semiconductor chip 11, thus, the bumps 12a and 12b and the chip alignment mark 15 are illustrated by a dotted line in FIG. 1.
Referring to FIG. 2, a plurality of wiring patterns 22a and 22b and a substrate alignment mark 25 may be formed on a surface of a substrate 21. The wiring patterns 22a may electrically connect the substrate 21 to the semiconductor chip 11, and the wiring patterns 22b may be dummy wiring patterns which are not related to the electrical connection. The substrate alignment mark 25 may be used to precisely arrange the semiconductor chip 11 in a correct position on the substrate 21.
Referring to FIG. 3, the semiconductor chip 11 may be arranged on the substrate 21, thereby forming a semiconductor package. Because the bumps 12a and 12b and the chip alignment mark 15 formed on the surface of the semiconductor chip 11 may be formed on a lower surface of the semiconductor chip 11, the bumps 12a and 12b and the alignment mark 15 are illustrated by a dotted lines in FIG. 3.
FIG. 4 is a cross-sectional view of a portion of the semiconductor package of FIG. 3 cut along a line IV-IV′. Referring to FIG. 4, the bumps 12a and 12b on the lower surface of the semiconductor chip 11 may be bonded to the wiring patterns 22a and 22b on the substrate 21. The semiconductor chip 11 and the substrate 21 may be electrically connected to each other by way of the bonding the bumps 12a to the wiring patterns 22a. The dummy bumps 12b may be bonded to the dummy wiring patterns 22b that may be formed on the surface of the substrate 21. The bonding between the dummy bumps 12b and the wiring patterns 22b may not electrically connect the semiconductor chip 11 to the substrate 21 but may reinforce the physical connection between the semiconductor chip 11 and the substrate 21.
Referring to FIG. 3, the chip alignment mark 15 is not disposed at the outer corner of the semiconductor chip 11 due to the presence of the dummy bumps 12b but is disposed in a portion of the semiconductor chip 11 which is interior to the bumps 12a and 12b. Accordingly, providing space for the routing wiring 13 may be difficult due to the chip alignment mark 15. Accordingly, the size of the semiconductor chip 11 may be required to be undesirably increased.